1. Field of the Technology
The present invention relates to a parallel type analog-digital converter capable of accurate and high speed analog-digital (hereinafter referred to as A/D) conversion.
An exemplary conventional parallel type analog-digital converter is constructed as shown in FIG. 1 to comprise comparators C.sub.1, C.sub.2 . . . C.sub.1023, the number of comparators being determined by the designed quantum levels, (that is in the case of 10 bit conversion the number of converter is 2.sup.10 -1=1023). The comparators C.sub.1, C.sub.2 . . . receive input analog signals on one of their input terminals, given through the input terminal V.sub.in, and on the other of their input terminals, each comparator receives different reference voltages from a voltage divider composed of series connected resistors R.sub.1, R.sub.2 . . . R.sub.1023 connected across positive and negative power source terminals V.sub.RH and V.sub.RG of the voltages V.sub.RH and V.sub.RG, respectively, the voltages being selected so as to be those of quantized levels. By such construction, all the comparators compare the input voltages with respective quantized levels of the reference voltages, in parallel and at the same time. Then, the output signals of the comparators C.sub.1 , C.sub.2 . . . are given to an encoder 1 which may include gate circuits for respective comparators C.sub.1, C.sub.2 . . . . And the encoded output is given to the output circuit 2 for conversion of the output levels. In the exemplary A/D converter as shown in FIG. 1, the resistors R.sub.1 to R.sub.1023 of the divider circuit have been of equal value, so that quantized voltage levels of equal voltage differences inbetween are produced, if the input current to the comparators C.sub.1 to C.sub.1023 would be negligibly small.
That is, if the current to flow into the comparators is negligibly small, the current I.sub.R in the series resistors R.sub.1 to R.sub.1023 is given as (provided that resistances thereof are equal and of the value R): ##EQU1## where n is the number of bits of the converted signal, and in this example, n=10. In this case, the voltages V.sub.RX given to the comparator input terminals from the X-th junction point of the voltage divider circuit are on a straight line (dotted line) on a graph shown in FIG. 2 and showing a V.sub.RX vs. serial number X relation.
However, in an actual converter, there are considerable input currents I.sub.i given to the input terminals of the comparators from the voltage divider circuit, and therefore the actual V.sub.RX vs. X curve becomes a curve as shown by a solid line in FIG. 2.
That is, the voltage V.sub.RX of the input terminal of the X-th comparator is given as ##EQU2## wherein 1.ltoreq.X.ltoreq.2.sup.n /2.
On the other hand, in the case of the dotted line (ideal case where I.sub.i =0), the voltage V.sub.RXO of the input terminal of the X-th comparator is given as EQU V.sub.RXO =(V.sub.RH -V.sub.RG)-R.multidot.I.sub.R .multidot.X (2),
wherein 1.ltoreq.X.ltoreq.2.sup.n /2.
Accordingly, the voltage difference .DELTA.V.sub.RX between the two voltage V.sub.RXO and V.sub.RX, which is the error between the ideal design for I.sub.i =0 and actual case, where the currents I.sub.i are not negligibly small, is given as ##EQU3## where 1.ltoreq.X.ltoreq.2.sup.n /2.
On the other hand in the range of X of EQU 2.sup.n /2.ltoreq.X.ltoreq.2.sup.n,
the voltage difference .DELTA.V.sub.RX should be represented as EQU .DELTA.V.sub.RX =.DELTA.V.sub.Ry ( 4),
where y=2.sup.n -X.
In the equation (3), at the value of EQU X=2.sup.n /2
the voltage difference .DELTA.V.sub.RX becomes maximum which is EQU .DELTA.V.sub.RX =1/2.multidot.R.multidot.I.sub.i (2.sup.2n -2.sup.2n-2 -2.sup.2n-1) (5).
In order to fulfil a lineality condition as an A/D converter, the error should be 1/2 LSB, (LSB is a value of the last sign bit, or quantum value), accordingly, EQU .DELTA.V.sub.RX .ltoreq.1/2LSB=1/2R.multidot.I.sub.R ( 6).
From the equations (5) and (6), the ratio I.sub.R /I.sub.i should fulfil the following condition: EQU I.sub.R /I.sub.i .gtoreq.2.sup.2n -2.sup.2n-2 -2.sup.n-1 ( 7).
Now, provided that I.sub.i =1 .mu.A, the current I.sub.R for the 10 bit A/D converter becomes as large as I.sub.R =786 mA. accordingly, when V.sub.RH -V.sub.RG =2V, (that is the peak to peak voltage of the analog input signal is 2 V.sub.pp), then the resistance of each resistors R.sub.X must be as low as 2.5.times.10.sup.-3 .OMEGA. in order to fulfill the above condition (7). Realization of such low resistances is not feasible, and moreover, the power consumption of the circuit is likely to become impractically large. In order to overcome such a problem, one solution may be to decrease the bias currents of the comparators. But a drastic decrease in the bias current can not be made in the case where the comparators for a high speed A/D converter are formed by emitter-coupled logic circuits. In that case the comparators are formed by using MOS transistors, the bias current can be made almost zero, but such MOS transistors have large offset voltages, and therefore an A/D converter of a very large bit number can not be formed.
Another proposal has been made to obtain an A/D converter as shown in FIG. 3, that is the reference power source for feeding current to the reference resistors is formed as a feed-back circuit in order to reduce the error due to the bias currents. In the circuit of FIG. 3, the encoder 1, comparators C.sub.1 to C.sub.n and divider circuit R.sub.1, R.sub.2, R.sub.3 . . . R.sub.n are the same as those designated by the same numeral and marks. A feed-back circuit 101 detects the voltage at the junction between the resistor R.sub.n-1 and R.sub.n and feeds a current to the series connection of the resistors R.sub.1 to R.sub.n, in a manner to equalize the voltage of the junction point with the reference voltage V.sub.ref. However, the problem in this circuit is that the output current of the feed-back circuit 101 is fed to all the series resistors R.sub.1 to R.sub.n of the divider circuit and, the higher the accuracy required the larger the current that is required.